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| STLC1511 NorthenLiteTM G.lite BiCMOS Analog Front-End Circuit PRODUCT PREVIEW s Wide transmit (~80dB) and receive (~69dB) dynamic range to limit the external filtering requirements for extended loop reach operation Programmable tx gain: 0 / -32dB in 2dB steps 14-bit D/A converter in transmit path Programmable rx gain: 0 /40dB in 0.5dB steps 12-bit A/D converter in receive path Integrated phase-locked loop with an externall LC or crystal oscillator Low power: 300mW @ 5.0V 64-pin TQFP package The STLC1511 transmit path consists of a 14-bit Nyquist rate D/A converter, followed by a programmable gain amplifier (TxPGA). The transmit gain is programmable from 0 to -32dB in 2dB steps. The STLC1511 receive path contains a buffer amplifier followed by a programmable gain amplifier (RxPGA), a low pass anti-aliasing filter, and a 12-bit Nyquist rate A/D converter. The RxPGA is digitally programmable from 0 to 40dB in 0.5dB steps. 2.0 PACKAGING AND PIN INFORMATION 2.1 STLC1511 Pin Allocation The pinout for the STLC1511 is depicted in Figure 1. TQFP64 ORDERING NUMBER: STLC1511 s s s s s s s 1.0 GENERAL DESCRIPTION The STLC1511 G.lite Analog Front End (AFE) chip implements the analog transceiver functions required in both a central office modem and a customer premise modem. It connects the digital modem chip with the loop driver and hybrid balance circuits. The STLC1511 has been designed with excellent dynamic range in order to greatly reduce the external filtering requirements at the front end. The AFE chip and its companion digital chip along with a loop driver, implement the complete G.992.2 DMT modem solution. Figure 1. STLC1511 pinout VSSDIG1 FRMCLK VCCTXPGA VEETXPGA QVEEDAC VDDESD2 TXDADC1 VSSESD2 VCCDAC VEEDAC TXSIN[1] TXSIN[0] RESETN 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VDDDIG1 CK35M DIGREF RXSOUT[0] RXSOUT[1] VSSDIGE1 VSSDIG2 VDDDIGE1 VDDDIG2 DTX DIGCLK ENB DRX VEEADC VCCADC QVEEADC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RXDCINP RXDCINN RXDCON RXDCOP RXINN RXINP RXOPIINN RXOPINP VCCRXPGA VEERXPGA VSSESD1 VDDESD1 QVEERX ADCDC3 ADCDC2 ADCDC1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 QVEEBIAS VEEBIAS VCCBIAS IREF50m V3P75V VCCPLL VEEPLL FREQ OSCNE OSCNB OSCPB OSCPE VCAP VDDPLL VSSPLL QVEEPLL QVEETX TQFP64 TXON November 2000 This is preliminary information on a new product now in development. Details are subject to change without notice. TXOP 1/31 STLC1511 2.2 Pin Description Table 1. details the pinout assignment for the STLC1511. The following list gives the different pin types for the STLC1511. s s s s VDD/VCC - 5V power supply VEE/VSS - Ground supply DO/DI - Digital Output/ Digital Input AO/AI/AIO - Analog Output/ Analog Input/ Analog Input-Output Table 1. Pin Assignement Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Pin Name VDDDIG1 CK35M DIGREF RXSOUT[0] RXSOUT[1] VSSDIGE1 VSSDIG2 VDDDIGE1 VDDDIG2 DTX DIGCLK ENB DRX VEEADC VCCADC QVEEADC ADCDC3 ADCDC2 ADCDC1 VSSESD1 VDDESD1 RXDCINP RXDCINN RXDCON RXDCOP RXINN RXINP Pin Type VDD DI DO DO DO VSS VSS VDD VDD DO DI DI DI VEE VCC VEE AIO AIO AIO VSS VDD AI AI AO AO AI AI Pad Type VDDCO TLCHT BT4CR BT4CR BT4CR VSSE VSSCO VDDE VDDCO BT4CR TLCHT TLCHT TLCHT VSSCO VDDCO VSSCO ANA ANA ANA VSSA VDDA ANA ANA ANA ANA ANA ANA Description 5V supply (digital) for ADC and DAC 35.328MHz serial interface clock input (also used in Test Mode to test PFD. See Table on page 21) 35.328/17.644MHz reference for Digital ASIC PLL Rx serial data (lsb) output Rx serial data (msb) output Ground for digital output drivers Ground supply for digital interface, serial interface 5 V supply for digital output drivers1 5 V supply for digital interface, serial interface Data Output for digital interface 35.328MHz clock input for digital interface Enable input for digital interface Data Input for digital interface Ground for ADC 5 V supply for ADC Quiet ground for ADC circuitry ADC reference decoupling (3.75 V) 0.1uF ADC reference decoupling (2.5 V) 0.1uF ADC reference decoupling (1.25 V) 0.1uF Ground for ESD ring 5 V supply for ESD ring RxPGA positive input from DC blocking capacitor RxPGA negative input from DC blocking capacitor RxPGA negative output to DC blocking capacitor RxPGA positive output to DC blocking capacitor Rx negative input (AC coupled) Rx positive input (AC coupled) 2/31 STLC1511 Table 1. Pin Assignement Pin # 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Pin Name RXOPINN RXOPINP VCCRXPGA VEERXPGA QVEERX QVEEPLL VSSPLL VDDPLL VCAP OSCPE OSCPB OSCNB OSCNE FREF VEEPLL VCCPLL V3P75V IREF50m VCCBIAS VEEBIAS QVEEBIAS QVEETX TXOP TXON VCCTXPGA VEETXPGA VDDESD2 VSSESD2 VCCDAC VEEDAC TXDADC1 Pin Type AI AI VCC VEE VEE VEE VSS VDD AO AIO AIO AIO AIO AI VEE VCC AIO AIO VCC VEE VEE VEE AO AO VCC VEE VDD VSS VCC VEE AIO Pad Type ANA ANA VDDCO VSSCO VSSCO VSSCO VSSCO VDDCO ANA ANA ANA ANA ANA ANA VSSCO VDDCO ANA ANA VDDCO VSSCO VSSCO VSSCO ANA ANA VDDCO VSSCO VDDA VSSA VDDCO VSSCO ANA Description Rx opamp negative input (must be DC coupled) Rx opamp positive input (must be DC coupled) 5V supply for RxPGA Ground for RxPGA Quiet ground for Rx circuitry Quiet ground for PLL circuitry Ground for Oscillator2 5 V supply for Oscillator2 Charge pump output to varactor Oscillator I/O (emitter) Oscillator I/O (base) Oscillator I/O (base) Oscillator I/O (emitter) 2.56 MHz PLL input reference/ 35.328 MHz clock input Ground for oscillator2 5 V supply for oscillator2 3.75V output from Bandgap to 0.22mF capacitor External resistor for bias current R=2.5V/ 50mA=50kohm 5V supply for biasing Ground for biasing Quiet ground for bias circuitry Quiet ground for Tx circuitry Tx positive output Tx negative output 5V supply for TxPGA Ground for TxPGA 5V supply for ESD ring Ground for ESD ring 5V supply for DAC Ground for DAC DAC reference (2.5V) 0.1uF 3/31 STLC1511 Table 1. Pin Assignement Pin # 59 60 61 62 63 64 Pin Name QVEEDAC RESETN TXSIN[0] TXSIN[1] FRMCLK VSSDIG1 Pin Type VEE DI DI DI DO VSS Pad Type VSSCO TLCHT TLCHT TLCHT BT4CR VSSCO Description Quiet ground for DAC circuitry ResetN for the AFE Tx serial data (lsb) input Tx serial data (msb) input Tx 4.416MHz frame clock reference output Ground (digital) for ADC and DAC <1>HCMOS5 guidelines are for 1 pair of power/ground for 4 output drivers (4mA) <2>Pins 35 and 43 are both connected to the analog VCC supplying the on chip oscillator. Similarly, Pins 34 and 42 are connected to analog VSS for the oscillator. Supply line inductance is reduced using two pads for VCC (and VSS) in this manner. At the board level, Pins 35 and 43 should be connected to analog VCC, and pins 34 and 42 should be connected to analog VSS. 3.0 FUNCTIONAL DESCRIPTION 3.1 General Functional Description The STLC1511 consists of the following functional blocks: s Transmit Signal Path s s Receive Signal Path Phase Lock Loop and Amplifier for an external oscillator. Bias Voltage and Current Generation Digital Interface Serial Interface struct a PLL that generates either a 17.644MHz/ 35.328 MHz clock from a 2.56 MHz reference clock when supplied with an external LC or crystal oscillator and tuning circuit. This clock is supplied to the both the transmit and receive converters, and the serial interface used to transfer the Rx/Tx data between the STLC1511 and digital chip. The STLC1511 also has the ability to be driven directly by an external 35.328MHz clock supplied to the FREF pin. The bias circuitry contains a bandgap voltage reference from which the converter references and analog ground voltage is generated. This block also generates an accurate current using an external resistor from which all of the STLC1511 circuits are biased. In addition, the bias circuitry also generates a 2.5V reference for the external Vco/Vcxo components and can be used for other external circuits if necessary. There is a 4 pin serial digital interface (DTX, DRX, DIGCLK, ENB) that loads a one of four 8-bit control register that controls all the programmable features on the STLC1511. Refer to "Digital Interface And Memory Map" on page 20 for more information on the programmability of the AFE. To facilitate data transfer between the STLC1511 and the digital ASIC (STLC1510), a 2-bit wide serial interface for the transmit path and a 2-bit wide serial interface for the receive path is incorporated into the AFE. This interface consists of two transmit pins (TXSIN[0:1]), two receive pins (RXSOUT[1:0]), and the necessary control signals (FRMCLK, CK35M) to transmit the required data. For more information See "Serial Interface" on page 18. s s s The transmit path contains the 14-bit digital to analog converter (DAC) necessary to generate the transmit signal from a 14-bit digital input word. This transmit signal is then scaled by the on chip programmable gain amplifier (TxPGA) from 0 to -32dB in 2dB steps. The scaled output signal is then driven off chip to the external filters and power amplifier (PA) which drives the DMT signal to the subscriber loop. The transmit path is fully differential but may be used single ended if both outputs from the TxPGA are terminated correctly. The receive path contains an optional unity gain buffer followed by a two stage programmable gain amplifier (RxPGA), a 1st order low pass anti-aliasing filter, and a 12-bit analog to digital converter (ADC). The RxPGA consists of two stages and the gain is digitally programmable from 0 to 40dB in 0.5dB steps. The receive path is fully differential but may be used single ended provided the other input to the RxPGA is grounded. The STLC1511 contains the circuits required to con- 4/31 STLC1511 Figure 2. The block diagram of the STLC1511 IR E F 5 0 U B and gap/ Bias Gen 14 -bit DAC V 3P 5V TXDADC1 0.22uF 50k 0.1uF fp=2M H z TXON TXOP dig I/F T X SIN [1:0] 2 14 4.416M FRM CLK 2.56M /35.328M 2.56M (O scillator Mode) FREF 35.328M (External Clock M ode) Serial I/F CK 35M 8/4 35.328M/ 17.622M 2 /3 /4 /8 PFD CP R X S O U T [1:0] 2 5 69 G D IG R E F 4.416M OSCPE OSCNE R X IN N G =1 + fp=2M H z R X IN P + + + R X O P IN P R X O P IN N D ig ital I/F D IG C L K ENB DRX DTX 12 12 -b it ADC + - ADCDC2 0.1uF ADCDC1 0.1uF ADCDC3 RXDCOP Shaded blocks are only usabe when the PLL is active. Crystal based external resonator for the CPE Mode, LC based resonator for the CO Oscillator Mode. 35.328 MHz external reference in CO External Clock Mode. 3.2 Receive Path Specifications Note: The first stage of the RxPGA provides a coarse gain of 0/20dB with a differential input or 6/26dB with a single ended input. The second stage implements a programmable gain from 0dB to 20dB in 0.5dB steps. 0.1uF RXDCON R E SE T N R X D C IN R X D C IP 0.1uF 0.1uF Re 90 so Ex n a tern to al r VCAP OSCNB OSCPB 5/31 STLC1511 Table 2. Receive Path Specifications Unless otherwise noted, typical specifications apply for VCC=5.0Volts, temperature=27xC, nominal process and current. Maximum and minimum performance is with VCC5%, -40= 3 min typ max Units Comments Where "D" is the binary value in b[7:6] of the control word. Includes Vcc, temperature, process, and frequency variation. 0 20 dB 6 26 dB 2nd Stage Absolute Gain1 2 Diff in to Diff out 4 0 =< D =< 40 D > 40 (0.5 * D) - 1.8 18.2 (0.5 * D) 20 (0.5 * D) + 0.8 20.8 dB Where "D" is the binary value in b[5:0] of the control word. Includes Vcc, temperature, process, and frequency variation. For more than a 1LSB change in the control word. Assumes a fixed Vcc, temperature, and frequency. For a fixed Vcc and frequency f (30kHz =< f =< 540kHz) relative to 27oC. For a fixed frequency f. (30kHz =< f =< 540kHz) and fixed temperature relative to Vcc=5.0V. For a fixed Vcc and temperature. relative to 30kHz relative to 155kHz Relative Gain Accuracy5 (relative to ideal gain of 0.5dB per LSB change.) -0.4 +0.4 dB Gain Variation with Temperature6 -0.3 +0.3 dB Gain Variation with Supply Voltage7 -0.1 +0.1 dB Gain Variation with Frequency8 30kHz =< f =< 120kHz 155kHz =< f =< 540kHz Gain Step Size For all steps except step 19.5 to 20dB (differential) or step 25.5 to 26dB (single ended) For step 19.5 to 20dB (differential) or step 25.5 to 26dB (single ended) -1.0 -1.0 0 0 dB 0.4 0.5 0.6 dB For a 1 LSB change in the control word at a fixed frequency f. (30kHz =< f =< 540kHz) 0.3 0.5 0.7 dB 6/31 STLC1511 Table 2. Receive Path Specifications Unless otherwise noted, typical specifications apply for VCC=5.0Volts, temperature=27xC, nominal process and current. Maximum and minimum performance is with VCC5%, -40= 250 15 252 19 nV ---------Hz at G=0dB at G=max11 Input Referred Noise9 10 11 at G=0dB at G=max11 250 20 252 27 250 20 252 27 nV ---------Hz Op amp Input Referred Noise9 10 11 10 15 nV ---------Hz spot noise @30kHz measured differentially at RXOPINP/N Output Signal to Distortion ratio Two tone (ATE testing)14 DS Multi tone15 30kHz =< f =< 120kHz 155kHz =< f =< 540kHz US Multi-tone16 30kHz =< f =< 120kHz 155kHz =< f =< 540kHz Input Impedance @pins RXOPINP/N @ pins RXINP/N @ pins RXDCIP/N DC Offset at output 60 63 63 63 63 66 69 69 69 69 dB For all RxPGA gain. Measured at output of ADC 250 1 1 1000 19 10 15 kW Rx Opamp input pins Rx PGA input pins Rx AC coupling pins measured at output of ADC mV Max Input Signal Level single ended differential 1.2 2.4 Vpe ak Vpe ak single-ended input differential input measured at any input (RXINP/N, RXOPINP/N, or RXDCINP/N) Time for PGA to settle to 3t accuracy after a change in the control word indicated by ENB going high. Settling Time17 300 nsec 7/31 STLC1511 Table 2. Receive Path Specifications Unless otherwise noted, typical specifications apply for VCC=5.0Volts, temperature=27xC, nominal process and current. Maximum and minimum performance is with VCC5%, -40= 100 530 mse c <1>For the purposes of this specification, a gain of 1 or 0dB is defined as the ratio of the full scale ADC output word to the input voltage at RXINP/RXINN when the input to the Rx path is at 2.4Vp differential measured between RXINP and RXINN. <2>For G.lite the STLC1511 will support both CO and CPE applications. As such it needs to support rates from 30kHz to 120kHz (CO Receive band) and 155kHz to 540kHz (CPE Receive band). <3>First stage gain is measured from RXINP/RXINN (differential input) to RXOP/RXON (differential output). Note that the gain from input to output can be adjusted for single ended input or differential input so that the output signal level at the output of the first stage of the PGA is at full scale. For a single ended input, the unused input, either RXINP or RXINN must be ac coupled to ground. <4>Second stage gain is measured from RXDCINP/RXDCINN (differential input) to the output of the ADC. <5>Will be tested at Vcc=5.0V, 27oC, and f=275kHz. <6>Will be tested at Vcc=5.0V and f=275kHz. <7>Will be tested at 27oC and f=275kHz. <8>Will be tested at Vcc=5.0V and 27oC. <9>Due to 1/f component, the spot noise is maximum at 30kHz over the bands of interest (US and DS). <10>Noise voltage is specified as the noise spectral density (en) at the input. Conversion to power spectral density is as follows en PSD = 10 x log --------- x 1000 100 <11>Input referred noise assumes that there is a 7dB cut in the first band of aliased noise which falls into the DMT frequencie s and that higher order aliases are negligible. For example, the single ended input referred noise for the maximum gain setting of 40dB is calculated as follows: 2 en = 2 2 1 1 + ----------------- ( 17nV Hz ) 2 + 17nV Hz + 250nV Hz ------------------------------ --------------------------------- 7 20 10 20 20 10 40 20 10 In general, the single ended input referred noise can be calculated as follows: en = 2 2 * 250nV Hz 1 1 + ----------------- ( 17nV Hz )2 + 17nV H z + ------------------------------------ ------------------------------ ( G 1 + G 2 ) 20 7 10 10G 1 20 10 10 where G1 and G2 are the gains of the first and second stages of the RxPGA respectively. Note that the assumption of a 7dB cut on the aliased noise is also used in the above formula and that all other higher order noise is sufficiently suppressed. <12>Note that the Rx path noise at 0dB gain is dominated by the quantization noise of the ADC and as such there is very little process, vcc, or temperature dependency and the variation from typical to maximum noise is only due to the Rx PGA. <13>At maximum gain PGA and Rx input opamp noise are the dominant contributors. <14>Two tone distortion is measured with two sinewaves with each sinewave at an amplitude of 1/2 full scale. Tone one is at f1=400kHz and tone two is at f2=500kHz. The two tone distortion requirement is measured from the rms voltage of a single signal tone to the peak rms voltage of the distortion products. <15>A multi-tone sine wave is used for the DS Multi-tone test. (The multi-tone signal will be 89 sinewaves equally spaced from 36*4.3125kHz to 125*4.3125kHz with a peak-to-rms ratio of 5.3V/V and an rms voltage equal to 1/5.3 of the peak full scale range of the PGA.) Multi-tone test measures the difference between the rms voltage of a single tone at the output to the rms voltage of the peak distortion product at the output in the band of interest. <16>A multi-tone sine wave is used for the US Multi-tone test. (The multi-tone signal will be 22 sinewaves equally spaced from 7*4.3125kHz to 28*4.3125kHz with a peak-to-rms ratio of 5.3V/V and an rms voltage equal to 1/5.3 of the peak full scale range of the PGA.) Multi-tone test measures the difference between the rms voltage of a single tone at the output to the rms voltage of the peak distortion product at the output in the band of interest. <17>The 1t settling time is roughly equivalent to the unity gain frequency of the PGA block. <18>The power up time is the time it takes the power up transient to dissipate such that the output SNR specification is met. This time is dominated by the coupling capacitors at pins RXINP/N and RXDCIP/N. 8/31 STLC1511 <19>Minimum DS frequency is 36*4.3125kHz=155.25kHz and as such the coupling capacitors between RXINP/N and RXDCIP/N must be such that the high pass pole is ~15kHz (typical). With a 1kW minimum input impedance at RXDCIP/N this gives a capacitor value of about 10nF. This gives a 1t settling time of 10ms.To guarantee 12-bit performance a minimum of 10t settling gives 100ms. <20>Minimum DS frequency is 7*4.3125kHz=30.1875kHz and as such the coupling capacitors between RXINP/N and RXDCIP/N must be such that the high pass pole is ~3kHz (typical). With a 1kW minimum input impedance at RXDCIP/N this gives a capacitor value of about 53nF. This gives a 1t settling time of 53ms.To guarantee 12-bit performance a minimum of 10t settling gives 530ms. 3.3 TRANSMIT PATH SPECIFICATIONS Table 3. Transmit Path Specifications Unless otherwise noted, typical specifications apply for VCC=5 Volts, temperature=27xC, nominal process and current. Maximum and minimum performance is with VCC 5%, -40 = -(2 * D) - 1.8 -33.8 -(2 * D) -32.0 -(2 * D) - 1.0 -31.0 dB Gain Step Size 1.8 2.0 2.2 dB Relative Gain Accuracy3 (relative to ideal gain of 2dB per step.) -0.4 +0.4 dB Gain Variation with Temperature4 -0.3 0.3 dB Gain Variation with Supply Voltage5 -0.1 0.1 dB Gain Variation with Frequency6 30kHz =< f =< 120kHz 155kHz =< f =< 540kHz -0.6 -1.0 0 0 dB 9/31 STLC1511 Table 3. Transmit Path Specifications Unless otherwise noted, typical specifications apply for VCC=5 Volts, temperature=27xC, nominal process and current. Maximum and minimum performance is with VCC 5%, -40 = 10 11 12 min typ max Units Comments For all TxPGA gains. 75 78 76 78 78 81 84 82 84 84 dB Measured differentially at TXOP/N TxPGA Gain = 0dB 30kHz =< f =< 120kHz 155kHz =< f =< 540kHz TxPGA Gain = min 30kHz =< f =< 120kHz 155kHz =< f =< 540kHz Output Signal to Noise and Distortion Ratio (DS) 13 14 TxPGA Gain = 0dB 30kHz =< f =< 120kHz 155kHz =< f =< 540kHz TxPGA Gain = min 30kHz =< f =< 120kHz 155kHz =< f =< 540kHz Output Signal to Noise and Distortion Ratio (US) 15 13 TxPGA Gain = 0dB 30kHz =< f =< 120kHz 155kHz =< f =< 540kHz TxPGA Gain = min 30kHz =< f =< 120kHz 155kHz =< f =< 540kHz Out of Band Noise 80 80 30 30 100 100 40 40 nV ---------Hz measured differentially at TXOP/N 74 73 53 53 80 79 59 59 dB measured differentially at TXOP/N 76 76 55 55 82 82 61 61 72 dB measured differentially at TXOP/N nV ---------Hz band from 550KHz - 2.2 MHz (fS/2) Maximum Output Signal @TXOP/N Load Resistance @ pin TXOP/N 500 Load Capacitance @ pin TXOP/ N 2.4 Vp differential output per output to 2.5V W per output to 2.5V 10 pF 10/31 STLC1511 Table 3. Transmit Path Specifications Unless otherwise noted, typical specifications apply for VCC=5 Volts, temperature=27xC, nominal process and current. Maximum and minimum performance is with VCC 5%, -40 = <1>For the purposes of this specification, a gain of 1V/V (i.e. 0dB) is defined as the ratio of the full scale DAC input word to the output voltage at TXOP/TXON when the output from the Tx path is at 2.4Vp differential measured between TXOP and TXON. <2>For G.lite the STLC1511 will support both CO and CPE applications. As such it needs to support rates from 30kHz to 120kHz (CPE Transmit band) and 155kHz to 540kHz (CO Transmit band). 275kHz is roughly in the middle of the required frequency range. <3>Will be tested at Vcc=5.0V, 27oC, and f=275kHz. <4>Will be tested at Vcc=5.0V and f=275kHz. <5>Will be tested at 27oC and f=275kHz. <6>Will be tested at Vcc=5.0V and 27oC. <7>Two tone distortion is measured with two sinewaves with each sinewave at an amplitude of 1/2 full scale. Tone one is at f1=400kHz and tone two is at f2=500kHz. The two tone distortion requirement is measured from the rms voltage of a single signal tone to the peak rms voltage of the distortion products. <8>A multi-tone sine wave is used for the DS Multi-tone test. (The multi-tone signal will be 89 sinewaves equally spaced from 36*4.3125kHz to 125*4.3125kHz with a peak-to-rms ratio of 5.3V/V and an rms voltage equal to 1/5.3 of the peak full scale range of the PGA.) Multi-tone measures the difference between the rms voltage of a single tone at the output to the rms voltage of the peak distortion product at the output in the band of interest. <9>A multi-tone sine wave is used for the US Multi-tone test. (The multi-tone signal will be 21 sinewaves equally spaced from 7*4.3125kHz to 28*4.3125kHz with a peak-to-rms ratio of 5.3V/V and an rms voltage equal to 1/5.3 of the peak full scale range of the PGA.) Multi-tone test measures the difference between the rms voltage of a single tone at the output to the rms voltage of the peak distortion product at the output in the band of interest. <10>Noise voltage is specified as the noise spectral density (en) at the output. Conversion to power spectral density is as follows: en PSD = 10 x log --------- x 1000 100 <11>The output referred noise voltage for the STLC1511 can be calculated as follows: 2 en = 2 2 * * ( G + 5.3 ) 20 ( 40nV Hz ) + ( 10 x 50nV Hz ) where G is the gain of the TxPGA expressed in dB. <12>The output referred noise of the Tx path at the 0dB gain setting is mainly due to the output referred noise of the DAC amplified by 5.3dB to the output of the chip. The DAC noise itself is made up of roughly equal contributions between quantization noise and thermal noise. It is only the thermal noise portion which will significantly change between a typical and worst case device. <13>The SNDR is the ratio of PSD of the signal to the PSD of the noise plus distortion. The input for this test is as described in h above scaled by the gain to produce a full scale output signal. <14>The effective noise plus distortion floor can be calculated from the SNDR based on the PSD of the output signal . ( 2.4 ( 5.3 x 540kHz - 155kHz ) ) PSD = 10 x log -------------------------------------------------------------------------------------------- x 1000 = - 52.7dBm Hz 100 So that for G=0, the effective noise plus distortion floor will be at -52.7dBm/Hz - 74dB = -126.7dBm/Hz and for G=max, the floor is at -52.7dBm/Hz -32dB (cutback) - 53dB = -137.7dBm/Hz <15>The SNDR is the ratio of PSD of the signal to the PSD of the noise plus distortion. The input for this test is as described in i above scaled by the gain to produce a full scale output signal. <16>1t settling time is roughly equivalent to the unity gain frequency of the PGA block. 2 11/31 STLC1511 3.4 Phase Lock Loop The STLC1511 has been intended for use in either the Central Office application (CO) using an external clock of 35.328MHz, in the Central Office application using an external 2.56Mhz clock and on-ship PLL , or in a Customer Premise Equipment application (CPE). In the CO application (External Clock Mode), the reference clock used for the converters and internally in the STLC1511 is provided by an external reference. In the CO application (Oscillator Mode), the STLC1511 provides the ability to drive a LC oscillator and generate the require clocks using an on-chip Table 4. PLL Application Modes1 FREF freq MHz 35.328 2.56 N/A 1.536 2.048 4.096 DIGREF freq MHz 35.328 17.664 35.328 35.328 35.328 35.328 PLL active? No Yes No Yes Yes Yes LC Osc freq MHz N/A 88.32 N/A N/A N/A N/A XTAL freq MHz N/A N/A 35.328 35.328 35.328 35.328 AFE Control 5 [b5:b0] 000000 001001 000110 011110 101110 111110 PLL. In the Customer Premise Equipment (CPE) application, the STLC1511 provides the crystal driver for use with a external crystal and feedback network. In the CPE application the tuning signal must be provided by the digital modem ASIC (STLC1510). While the above descriptions highlight the intended applications, the STLC1511 also has the flexibility to provide a PLL function when used with a different reference frequency and external 35.328MHz crystal. Table 4 highlights the different PLL modes for the STLC1511. Description CO External Clock Mode2 CO Oscillator Mode CPE Mode PLL Misc. 1 PLL Misc. 2 PLL Misc. 3 <1>Presently only applications described in this table are supported. <2>The clock jitter specification for an externally supplied DAC or ADC clock (on pins FREF when in CO External Clock mode) is the same as the jitter specification for the PLL. 3.4.1 Central Office (External Clock Mode) In CO External Clock Mode the 35.328MHz reference clock on pin FREF is divided down and used in both the TX and RX converters. In this mode of operation, the PLL and oscillator driver are powered down. External Clock Mode is selected by setting b5:b0 of register "AFE Control 4" to "000000". See section 3.7 for more information. 3.4.2 Central Office (Oscillator Mode) In Oscillator Mode the 2.56MHz reference clock on pin FREF is used as the reference clock for the STLC1511 PLL. This clock is used to lock the LC oscillator frequency to 88.32MHz which is further divided down to provide the sampling clocks to both the TX and RX converters and passed to the digital ASIC STLC1510 as its PLL reference on the pin DIGREF. The clock supplied to the digital ASIC STLC1510 via DIGREF is running at a rate of 17.664MHz in this mode. details the CO PLL and oscillator performance when connected as shown in Figure 3, "CO Frequency vs. Tuning Voltage". CO Oscillator mode is selected by setting b5:b0 in register "AFE Control 5" to "001001". See section "Digital Interface And Memory Map" on page 20 for more information. 12/31 STLC1511 Table 5. CO PLL Specifications Unless otherwise noted, typical specifications apply for VCC=5.0 V, temperature=25xC, nominal process and bias current. Maximum and minimum performance is with VCC 5%, -40 =< Tjunction =< 105xC, and worst case process. Description Reference Clock Frequency Output Clock Frequency LC Frequency Tuning Rangee Oscillator Signal Level Power Up Time VCO Gain Vco gain (LC) Charge Pump Current Input Impedance @OSCPB and OSCNB1 Output Impedance @OSCPE and OSCNEa CO Phase Noise at fs2 5KHz offset 10kHz offset 20kHz offset 30kHz offset 100kHz offset 200kHz offset 300kHz offset 400kHz offset 500kHz offset 84 min typ 2.56 17.644 88.32 94 max Units MHz MHz MHz Comments on pin FREF at pin DIGREF Assumes 2% capacitors. 200 200 500 mVp msec see CAPTION FIGURE 4 on page 14 5.0 180 5.4 200 6 220 MHz/V mA see TITLE 3 3.4.3 on page 16 see TITLE 3 3.4.3 on page 16 89 91 97 101 120 129 133 137 141 dBc/Hz Phase noise at DIGREF output (i.e. 17.664MHz) in CO Oscillator mode. <1>Input and output impedance measured with 50kW from OSCPB to Vcc and OSCNB to Vcc <2>For inband noise, phase noise at multiples of 4.3125kHz will rms add to degrade the inband SNR. Similarly, for out of band signals, phase noise will rms add depending on the offset between the carrier and the band of interest to reduce the SNR. For example, noise contributions on carriers from 34 to 127 will rms add to degrade the SNR on the edge of the US band (carrier 26). 13/31 STLC1511 Figure 3. CO Frequency vs. Tuning Voltage AFE C h arge P u m p VC AP Ce vcc osc_o utp I O SC PE O SC PB C 1n L L C 1n 2.5v O SCN B Cv C e=100pF C =27pF L=56nH C v=10pF R b=4k R x=1M vcc I O SC NE o sc_ou tn Ce Figure 4. CO Frequency vs. Tuning Voltage 14/31 STLC1511 Figure 5. Oscillator Input Impedence Figure 6. Oscillator Output Impedence 15/31 STLC1511 3.4.3 Customer Premise Equipment In CPE mode, the STLC1511 provides the amplifier required to power the off-chip crystal oscillator. The crystal oscillator runs at a frequency of 35.328 MHz (series resonant) which is further divided down to provide the sampling clocks to both the TX and RX converters and passed to the STLC1510 as its PLL reference on the pin DIGREF. Note that in CPE mode, neither the PLL or the pin FREF is used (FREF should be connected to either Vdd or Vss) and that the tuing for the external oscillator is generated on the STLC1510. The following table details the CPE oscillator performance when connected as shown in Figure 3. on page 14. CPE mode is selected by setting b5:b0 in register "AFE Control 5" to "001110". See section "Digital Interface And Memory Map" on page 20 for more information. Note the reference design provided is based on a Reeves Hoffman fundamental Mode AT cut crystal at 35.328MHz.(Crystal accuracy@+/-50ppm (+/-15ppm calibration tolerance, +/-15ppm 10 year aging, +/-20 ppm temperature variation, Rs@15 max, Cm@15fF max, and Co@3.5pF typ (assumes a HC49/43 package).) Table 6. CPE PLL Specifications Unless otherwise noted, typical specifications apply for VCC=5.0 V, temperature = 25xC, nominal process and bias current. Maximum and minimum performance is with VCC 5%, -40 =< Tjunction =< 105xC, and worst case process. Description Output Clock Frequency Crystal Accuracy1 2 Crystal Frequency Tuning Range2 3 Oscillator Signal Level Power Up Time VCO Gain Vcxo gain (crystal) Input Impedance @OSCPB and OSCNB4 Output Impedance @OSCPE and OSCNE4 CPE Phase Noise at fs5 10Hz offset 20Hz offset 40Hz offset 60Hz offset 80Hz offset 100Hz offset 200Hz offset 400Hz offset 600Hz offset 800Hz offset 1000Hz offset -51.9 -57.9 -63.9 -67.5 -69.9 -71.9 -77.9 -83.9 -87.5 -89.9 -91.9 dBc/Hz 1.4 -50 -125 200 5 1.6 min typ 35.328 +50 +125 500 10 1.7 max Units MHz ppm ppm mVp msec see TITLE 2 3.5 on page 18 KHz/V see TITLE 3 3.4.3 on page 16 see TITLE 3 3.4.3 on page 16 Phase noise at DIGREF output (i.e. 35.328MHz) in CPE mode. Comments at pin DIGREF crystal accuracy for CPE. Occurs at CPE. Assumes CO is free running <1>For the CPE side a crystal oscillator will be used. <2>50ppm accuracy is divided as 15ppm for manufacture, 15ppm for 10 year drift, and 20ppm for temperature variation. <3>Worst case for tuning is when CO is not locked and CPE must retime from CO. Nominally the tuning range for the CO is 50ppm, so that if the CO is free running, the CPE must tune over the CO inaccuracy and the CPE crystal inaccuracy as well. <4>Input and output impedance measured with 50kW from OSCPB to Vcc and OSCNB to Vcc <5>For inband noise, phase noise at multiples of 4.3125kHz will rms add to degrade the inband SNR. Similarly, for out of band signals, phase noise will rms add depending on the offset between the carrier and the band of interest to reduce the SNR. For example, noise contributions on carriers from 34 to 127 will rms add to degrade the SNR on the edge of the US band (carrier 26). 16/31 STLC1511 Figure 7. Typical CPE Oscillator Configuration V C AP A FE Ce v cc o sc_ o u tp I O SC PE O SC PB C CPE D IG IT A L A SIC C urre nt 5v O u tp ut 2.5 v Cv 5v o sc_ ou tn O SC N B O SC NE C I Ce Lm Cm Co Rm C m = 15fF C =3.5pF R m = 1 5 C e= 180pF C =82pF C v= 20pF R b= 4k R x= 1M C lo ck R eco v ery Figure 8. CPE Frequency vs. Tuning Voltage v cc C rystal M odel 17/31 STLC1511 3.5 Reference Voltages Table 7. Reference Voltages/Currents Unless otherwise noted, typical specifications apply for VCC = 5.0 V, temperature=25xC, nominal process and bias current. Maximum and minimum performance is with VCC 5%, -40 = 2.425 2.5V 2.575 50 measured at TXDADC1 measured at TXDADC1 assume 2% 49 50 0.22 51 3.6 Serial Interface The serial interface on the AFE provides for transmission of transmit and receive data between the STLC1511 and digital modem ASIC. This is accomplished with a two bit wide data stream in each direction plus the appropriate clocks. The data for the transmit path is input to the AFE on the TXSIN[1:0] pins and the data for the receive path is output on the RXSOUT[1:0] pins. The serial interface also consists of a 35.328MHz clock (CK35M) which is generated in the STLC1510 and is used to retime the Tx data sent to the STLC1511. It is also used in the STLC1511 to retime the Rx data before it is sent to the digital chip. A 4.416MHz pulse is also output from the STLC1511. This pulse on pin FRMCLK is used to indicate the start of the output and input data words. The alignment of the data to the FRMCLK signal is shown below. A diagram of this interface is show in Figure 11. Note the MSB of each of the 8-bit registers is transferred first (MSB = b15/ b7.) Note that the data word used by the converters is in 2's complement notation. 18/31 STLC1511 Figure 9. Serial Interface Block Diagram T X S IN [1:0] 2 S DATA SO U T 8-bit Shift Register (x2) CK O U T[15:0] 14 Out[15:0] D Q (x14) to DAC parallel input (N ote: DAC input is sampled on posedge C KDAC) 14 F RM C LK Q D Q D Q D Q D Q D CKDAC (4.416M Hz Clock from PLL) CK 35M (4.416MHz Clock from PLL) CK ADC Q D Q D Q D (4 Dff to align data edges as required) LD 2 LD S OU T SD ATA 8-bit Shift Register (x2) CK D ATA [15:0] 12 Data[15:0] Q D (x12) 12 R X S O U T[1:0] 2 Q D (x2) from ADC parallel output (Note: ADC output changes on posedge of C KADC ) CK35M FRM CLK TXSIN [0] TXSIN [1] RXSOUT[0] RXSOUT[1] C KDAC CK ADC a5 msb a4 a12 a3 a11 a2 a10 a1 a9 lsb a8 a7 a6 b3 msb b2 b10 b1 b9 lsb b8 b7 b6 b5 b4 D ata clocked out by AD C on this edge D ata sam pled by D AC on this edge 3.6.1 ADC Clip Indicator Normally, the receive signal level is set such that the input to the STLC1511 plus the RxPGA gain will not saturate the input to the ADC converter (for maximum ADC input levels). If the input signal is too large however and causes the ADC to clip, the STLC1511 will report to the digital chip that a clip has occurred. This is accomplished by forcing the output data stream supplied to the digital chip to either "7FFF" hex for an out of range positive input or to "8000" hex for an out of range negative input. This is highlighted in Figure 10. 19/31 STLC1511 Figure 10. Clip Indicator Output. C K 35M FRM C L K P ositive C lip R XSO U T[0] b[7:0]= FF b[15:8]= 7F R XSO U T[1] N egative C lip RXSO U T [0] b[7:0]= 00 b[15:8]= 80 RXSO U T [1] Bit 0 in the "AFE Status" register is also set to high when a clip occurs. This bit can be disabled via the control interface, see Table 8 on page 21 for more details. This bit is cleared on read. For more information see "Digital Interface And Memory Map" on page 20. 3.6.2 Tx Loop Back When bit "b1" of register "011" (AFE Control 4) is asserted the data received on the TXSIN[1:0] pins is converted to parallel and then sent directly to both the DAC and the RX parallel data input replacing the usual data from the ADC. This allows a "loop back" to the input TX data from TXSIN[1:0] to the RXSOUT[1:0] to help the testability of the serial interface. 3.7 Digital Interface And Memory Map All parametric specifications in Table 2 on page 6 and Table 3 on page 9 are guaranteed assuming that the Digital Interface is inactive. Figure 11. Digital Interface Timing Diagram All parametric specifications in Table 2 and Table 3 are guaranteed assuming that the Digital Interface is inactive. The digital interface operates at a rate of 35.328 MHz. The companion DSP chip, STLC1510, sources the 35.328 MHz clock used by the AFE. To minimize the impact of digital noise on the STLC1511, this supplied clock is gated, and is only enabled during data transfers and during reset. The clock does not need to be present in order to reset the chip. The processor interface consists of four pins: 1) the 35.328 MHz gated clock (DIGCLK); 2) a data in port for data transfers (DRX); a data out pin for data transfer (DTX); and 4) a chip select pin (ENB). There are a total of 12 bits which are serially transmitted between the STLC1510 and AFE during data transfers. The gated clock lasts for a duration of 12 clock cycles. This 12 cycle interaction consists of a R/ W bit, a 3 bit address, and a 8 bit data word. The format for this serial transaction is given below in Figure 11. DIGCK (35MHz) ENB ADDRESS [a2:a0] DRX R/W DATA[b7:b0] for write access DTX DATA[b7:b0] for read access 20/31 STLC1511 During a transaction, the first bit sent to the AFE determines the type of transaction, R/W="1" corresponds to a read transaction while R/W="0" corresponds to a write transaction. The next three bits, address[a2:a0], determine which of the 8 AFE registers will be accessed (Table 8). This is followed by the 8-bit data word. In both Read and Write transactions, bit 0 (LSB) of the serially transferred 8-bit word is clocked from the data source first (the data source being the external DSP during Write transactions; the STLC1511 during Read transactions). The definition of these fields within the 8-bit word is Table 8. AFE Register Map Summary Addr [a2:a0] 000 Name STLC1511 Control 1 (Rx PGA Gain) STLC1511 Control 2 (Tx PGA Gain) STLC1511 Control 3 (Power Down Reg) D7 D6 D5 D4 D3 D2 D1 D0 Type RW outlined below in Table 8 and in the detailed register maps following. When the voltage on the RESETN pin is low, the bits in the control register will be reset as per defined in the detailed register maps. For a write operation, the data on the DRX pin is latched into the STLC1511 on the negative edge of the DIGCLK signal. The data should change state on the positive edge of the clock. For a read operation, the data on the DTX pin is output on the positive edge of the clock on pin DIGCLK. Rx PGA Gain 001 not used Tx PGA Gain RW 010 not used Rx Opa mp Pow er Dow n DIV Output (Test mode) not use d Rx Pow er Dow n Tx Pow er Dow n RW 011 STLC1511 Control 4 (Misc. Control) not use d PLL PFD inpu t sel Tx Loo p back Clip Indic ator ena ble RW 100 AFE Control 5 (PLL Control) not use d DIGREF Ena ble FREF Mode PLL Mod e Osc Mod e1 Clock Source Control R/W 101 110 111 not used not used AFE Status not used not used not used Clip Stat us R <1>Presently there is no difference in the oscillator driver between Oscillator Mode and CPE modes so this bit is unused. However, it may be required in the future and should be programmed correctly in case needed. 21/31 STLC1511 Table 9. Detailed Register Map: AFE Control Byte 1 Title: Label: Address: Description: Bit Label RX Gain AFE Control 1 (Rx PGA Gain) Rx Gain 000 Rx PGA Gain Setting Bit(s) b5-b0 Value 0SDS40 DS40 00 01 10 11 Bit Description Gain=D*0.5 dB Gain=20 dB Gain=0 dB Gain=20 dB Gain=6 dB Gain=26 dB Reset 000000 Access Type: Bits Used: R/W 8 RX Gain MSB b7-b6 0 Table 10. Detailed Register Map: AFE Control Byte 2 Title: Label: Address: Description: Bit Label TX Gain AFE Control 2 (Tx PGA Gain) Tx Gain 001 Tx PGA Gain Setting Bit(s) b4-b0 Value 0SDS16 DS16 Bit Description Gain= -D*2 dB Gain=-32 dB Reset 00000 Access Type: Bits Used: R/W 5 not used b7-b5 000 Table 11. Detailed Register Map: AFE Control 3 Title: Label: Address: Description: Bit Label Tx Power Down1 Rx Power Down2 not used b0 AFE Control 3 (Power Down Reg) Power Down 010 Power Down Register Bit(s) 0 1 0 1 Value Bit Description Power up transmit path Power down transmit path Power up receive path Power down receive path 1 Reset Access Type: Bits Used: R/W 3 b1 1 b2 0 22/31 STLC1511 Table 11. Detailed Register Map: AFE Control 3 Title: Label: Address: Description: Bit Label Rx Opamp Power Down not used b3 AFE Control 3 (Power Down Reg) Power Down 010 Power Down Register Bit(s) 0 1 Value Bit Description Power up RxPGA Power down RxPGA 1 Reset Access Type: Bits Used: R/W 3 b7-b4 0 <1>During power down the Tx serial interface is also disabled and TXSCLK is tristated. <2>During power down the Rx serial interface is also disabled and RXSCLK and RXSOUT[1:0] are tristated Table 12. Detailed Register Map: AFE Control 4 Title: Label: Address: Description: Bit Label Clip Indicator Enable b0 AFE Control 4 (Misc. Control) Misc Control 011 Mode Control/Misc. Bit(s) 0 1 0 1 Value Bit Description Clip indicator disabled Clip indicator enabled Normal operation Test mode. Tx data sent to serial I/F is muxed to Rx input and trasmitted via the serial I/F Source of PLL phase-frequency detector feedback input. Output of feedback dividers. Signal on FREF is sent directly to PFD (ref input) and signal on pin CK35M is sent directly to PFD (vco input). normal operation Output of DIV69 counter is output to DIGREF pin Output of DIV2/3/4/8 counter is output to DIGREF pin Output of DIV5 counter is output to DIGREF pin 1 Reset Access Type: Bits Used: R/W 5 Tx Loop back b1 0 PLL Phase/Freq Input Select (Test Mode) b2 0 1 0 DIV Output (Test Mode only) b3-b4 00 01 10 11 0 not used b7-b5 000 23/31 STLC1511 Table 13. Detailed Register Map: AFE Control 5 Title: Label: Address: Description: Bit Label Clock Source Control AFE Control 5 (PLL Control) PLL Control 100 PLL Control Register Bit(s) b0-b1 00 Value Bit Description (CO External Clock Mode.) Output of clock selection MUX is from FREF pin. This state also powers down the PLL and oscillator driver. (CO Oscillator Mode.) Output of clock selection MUX is from output of divide by 5. (CPE Mode). Output of clock selection MUX is from output of oscillator driver. (Other CPE Mode). Output of clock selection MUX is from output of oscillator driver. (CO Oscillator mode.) AFE is configured to drive external 88.32MHz LC oscillator. (CPE mode.) AFE is configured to drive external 35.328MHz crystal oscillator. PLL active (PFD,CP active) PLL Inactive (PFD,CP powered down) FREF frequency is 2.56MHz FREF frequency is 1.536MHz FREF frequency is 2.048MHz FREF frequency is 4.096MHz DIGREF Output pin tristated DIGREF Output pin active 1 00 Reset Access Type: Bits Used: R/W 7 01 10 11 OSC Mode1 b2 0 1 PLL Mode b3 0 1 00 01 10 11 0 1 0 FREF Mode2 b5-b4 00 DIGREF Enable b6 1 reserved b7 0 <1>Presently there is no difference in the oscillator driver between CO Oscillator and CPE modes so this bit is unused. However, it may be required in the future and should be programmed correctly in case needed. <2>For FREF at 2.56MHz (b5:b4 = "00"), the compare frequency for the PLL is at 1.28MHz. For all other FREF modes the compare frequency is at 512kHz. 24/31 STLC1511 Table 14. Detailed Register Map: not used Title: Label: Address: Description: Bit Label not used Bit(s) b7-b0 Value Bit Description Reset 00000000 AFE Control 6 (Misc Control 2) Misc Control 2 101 Access Type: Bits Used: R/W 0 Table 15. Detailed Register Map: not used Title: Label: Address: Description: Bit Label not used Bit(s) b7-b0 Value Bit Description Reset 00000000 110 not used Access Type: Bits Used: R/W 0 Table 16. Detailed Register Map: AFE Status Title: Label: Address: Description: Bit Label Clip Status? b0 AFE Status AFE Status 111 AFE Read only Status Bit(s) 0 1 Value Bit Description A/D clip not detected A/D clip detected 0 Reset Access Type: Bits Used: R 2 not used b7-b2 000000 25/31 STLC1511 3.8 TIMING Table 17. describes the timing relationships between important signals. Table 17. Timing Symbol tSENB tHENB tSDRX tHDRX tDDTX tSCK35 tHCK35 tDRX tDFC tDDRCK35 tRDIGREF tFDIGREF Parameter ENB falling to DIGCLK rising ENB rising to DIGCLK falling Data in valid to DIGCLK falling DIGCLK falling to Data in hold DIGCLK rising to Data out valid TXSIN[1:0] valid to CK35M falling CK35M falling to TXSIN[1:0] hold CK35M rising to RXSOUT[1:0] valid CK35M rising to FRMCLK valid DIGREF rising to CK35M rising DIGREF rise time (20% to 80%) DIGREF fall time (80% to 20%) 10 1 1 2 2 Spec Min 1 1 2 2 Typ 1 5 5 5 5 5 5 5 5 5 12 2 2 10 10 20 3 3 10 Spec Max Unit s ns ns ns ns ns ns ns ns ns ns ns ns <1>Load on all output pads assumed to be < 25pF.This gives a delay through the TLCHT pad of approximately 5ns. 3.9 POWER UP RESET When the voltage on the RESETN pin is low the bits in the control register will be reset as per the detailed register maps in "Digital Interface And Memory Map" on page 20. In addition, digital output pins, DTX, FRMCLK, and RXSOUT[1:0] are high impedance. The other digital outputs are always as defined in Table 1 on page 2. 26/31 STLC1511 4.0 PACKAGE INFORMATION, SUPPLY RATINGS, AND OPERATING ENVIRONMENT 4.1 The thermal impedance The thermal impedance of the package is about 64 C/W for the following conditions Table 18. Board Assumptions: PC Board Ambient Temperature Air Flow Power Dissipation 6 layer, 1oz copper 850C natural convection 300mW Table 19. Board Assumptions: PC Board Ambient Temperature Air Flow Power Dissipation 6 layer, 1oz copper 850C natural convection 300mW COMMENT ON RELIABILITY: The maximum continuous junction temperature for this part while meeting 20 year reliability is 125 C. 4.2 Environmental Conditions Table 20. Environment conditions Ta Long-Term (Continuous) Ta Short-Term1 -40 to +80 0C -40 to +85 0C <1>Short-term is defined as no greater than 96 consecutive hours and 15 days per year. 4.3 Power Supply Input Limits Table 21. defines the maximum and minimum power supply requirements to meet specifications as outlined in section 3.2 and 3.3. Table 21. Power Supply Limits Limits Parameter min Positive Supply Voltage 4.75 typ 5 max1 5.25 Volts Unit Conditions 27/31 STLC1511 Table 21. Power Supply Limits Limits Parameter min Tx Powered Up CO Oscillator mode CO External Clock mode CPE mode Tx Powered Down CO Oscillator mode CO External Clock mode CPE mode Tx Powered up CO Oscillator mode CO External Clock mode CPE mode Tx Powered Down CO Oscillator mode CO External Clock mode CPE mode typ max1 Unit Conditions 65 60 65 41 36 41 71 66 71 45 39 45 mA Includes 4mA for digital supplies and digital I/O 325 300 325 200 175 200 373 347 373 237 205 237 mW Includes 20mW for digital supplies and digital I/O <1>Maximum current assumes a 7% increase due to process/temperature/Vcc plus the variation in the external 50k resistor (assumed 2%) connected to IREF50u. For this table the total variation is assumed at 9%. 4.4 Power Supply Noise Table 22. Power Supply Noise Noise Band Maximum 5V Supply Noise Spectral Density Max 5V Supply Noise (Over noise band) 1.0mVrms 30kHz < f < 112kHz 146kHz < f < 547kHz 1.4Vrms/rtHz @ 112kHz, rising 6dB per octave for decreasing frequency 1.0Vrms/rtHz @ 146kHz, dropping 6dB per octave to 0.25Vrms/rtHz @ 547kHz 0.30mVrms 4.5 Absolute Maximum Ratings The following table describes the maximum and minimum voltage ratings Table 23. Maximum and minimum voltage ratings pin all VCC pins all other pins 6.5V VCC+0.4 Maximum -0.5V -0.4 Minimum 28/31 STLC1511 4.6 Pin DC Electrical Specification Table 24. General Interface Electrical Characteristics Parameter Iil Iih Ioz Low level input current High level input current Tri-state output leakage1 Conditions Vi=0V Vi=Vcc Vo=0V or Vcc Min Typ Max 1 1 1 Unit A A A <1>The leakage currents are generally very small, < 1nA. The value given here, 1mA, is a maximum that can occur after an ESD stress. BT4CR is a CMOS tristate 4mA output pad buffer with slew rate control. Table 25. CMOS Output Pad (BT4CR) DC Electrical Characteristics 1, 2 Parameter Vol Voh Low level output voltage High level output voltage Conditions Iol=4mA Ioh=4mA 0.9*Vdd5 Min Typ 0.4 Vdd5 Max Unit V V <1>Characterized for VCC=3.0 to 3.6V. This pad must be characterized at VCC=5.0V+-5% and the table updated <2>Assumes a 200mV voltage drop in both supply lines. This will not be the case in the STLC1511. Table 26. TTL Input Pad (TLCHT) DC Electrical Characteristics1, 2 Parameter Vil Vih Vilhyst Vihyst Low level input voltage High level input voltage Low level Threshold input falling High level Threshold input rising 2.0 0.9 1.4 1.45 1.9 Conditions Min Typ Max 0.8 Unit V V V V <1>Characterized for VCC=3.0 to 3.6V. This pad must be characterized at VCC=5.0V+-5% and the table updated <2>Assumes a 200mV voltage drop in both supply lines. This will not be the case in the STLC1511. 29/31 STLC1511 4.7 Package The STLC1511 will be packaged in a 64pin 10x10x1.4mm Thin Quad Flat Pack (TQFP) package. DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.40 0.05 1.35 0.18 0.12 1.40 0.23 0.16 12.00 10.00 7.50 0.50 12.00 10.00 7.50 0.60 1.00 0(min.), 7(max.) 0.75 mm TYP. MAX. 1.60 0.15 1.45 0.28 0.20 0.002 0.053 0.007 0.055 0.009 MIN. inch TYP. MAX. 0.063 0.006 0.057 0.011 OUTLINE AND MECHANICAL DATA 0.0047 0.0063 0.0079 0.472 0.394 0.295 0.0197 0.472 0.394 0.295 0.0157 0.0236 0.0295 0.0393 TQFP64 D D1 A D3 A1 48 49 33 32 0.10mm Seating Plane A2 B E3 E1 64 1 e 16 17 C L1 E L K TQFP64 30/31 B STLC1511 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (R) 2000 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 31/31 |
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